1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to a semiconductor memory device with a test circuit which can simultaneously test a plurality of memory cells.
2. Description of the Background Art
FIG. 19A is a block diagram showing a structure of a conventional semiconductor memory device with a test circuit. The semiconductor memory device shown in FIG. 19A is described, for example, in ISSCC85 Dig. of Tech. Papers pp. 240-241 by M. Kumanoya, et al..
In FIG. 19A, a memory array 1 comprises a plurality of memory cells arranged in a plurality of rows and columns. This memory array 1 is divided into four memory array blocks B1 to B4. Input/output line pairs I01 to I04 are provided corresponding to the memory array blocks B1 to B4, respectively. The memory array 1 is provided with row decoders 2a and 2b for selecting a row, and with column decoders 3a and 3b for selecting a column.
On the other hand, address signals A0 to An are applied to an address buffer 4 from outside. Further, an external row address strobe signal RAS, an external column address strobe signal CAS and an external write enable signal WE are applied to a RAS buffer 5, a CAS buffer 6 and a WE buffer 7, respectively.
The address buffer 4 is responsive to the strobe signal RAS from the RAS buffer 5 to apply the address signals A0 to An from outside to the row decoders 2a and 2b as row address signals. The row decoder 2a is responsive to the row address signals for selecting one row in each of the memory array blocks B1 and B3. The row decoder 2b is responsive to the row address signals for selecting one row in each of the memory array blocks B2 and B4. Furthermore, the address buffer 4 is responsive to the strobe signal CAS from the CAS buffer 6 for applying the address signals A0 to An from outside to the column decoders 3a and 3b as column address signals. The column decoder 3a is responsive to the column address signals for selecting one column in each of the memory array blocks B1 and B2. The column decoder 3b is responsive to the column address signals for selecting one column in each of the memory array blocks B1 and B2. The column decoder 3b is responsive to the column address signals for selecting one column in each of the memory array blocks B3 and B4.
In normal reading or writing, a switch 9 is switched to the side of a contact a. In reading, one memory cell is selected in each of the memory array blocks B1 to B4. Data having been stored in the four selected memory cells are applied to preamplifiers PA1 to PA4 through the input/output line pairs I01 to I04, respectively. One of transistors T1 to T4 is turned on by a block selector 8. This permits the data amplified by any one of the preamplifiers PA1 to PA4 to be outputted as output data D.sub.out through the switch 9 and an output buffer 11 to the external.
Also in writing, one of the transistors T1 to T4 is turned on by the block selector 8. This permits input data D.sub.in having been externally applied to a Din buffer 12 to be written in a selected memory cell in any one of the memory array blocks through the corresponding input/output line pair I01 to I04. Meanwhile, the selection of reading or writing is made by the external write enable signal WE applied to the WE buffer 7.
In the semiconductor memory device of FIG. 19A, a multi-bit test mode is available for reducing test time. This multi-bit test mode is controlled by externally applying a test enable signal TE to a test control circuit 10. In testing, the switch 9 is switched to the side of a contact b by the test control circuit 10.
In writing of test data, all of the transistors T1 to T4 are turned on by a multi-bit write control circuit 13. This allows externally applied test data to be simultaneously written in the memory array blocks B1 to B4 through the D.sub.in buffer 12 and the input/output line pairs I01 to I04.
On the other hand, in test data reading, test data having been read out of the memory array blocks B1 to B4 through the input/output line pairs I01 to I04 are amplified by the preamplifiers PA1 to PA4 before entered into an exclusive OR circuit 14. If the four data match with each other, the exclusive OR circuit 14 outputs a flag of "H", or otherwise if any one mismatch exists between the four data, it outputs a flag of "L". The output of the exclusive OR circuit 14 is extracted to the outside through the switch 9 and the output buffer 11.
More specifically, if test data of four "L"-bits have been entered into the memory array 1, outputs of the preamplifiers PA1 to PA4 will be all "L" except there exists any defective memory cell in the memory array 1, so that the exclusive OR circuit 14 outputs a flag of "H". Also, when test data of four "H"-bits have been entered, a flag of "H" will be outputted likewise if there are no deficiency in all of the memory cells. By contrast, if there exists any deficiency in the memory cells of the memory array 1, the read-out data will contain "H" and "L" mixed up even when the same data have been written in all the memory cells. This leads to output of a "L" flag by the exclusive OR circuit 14.
According to the multi-bit test mode above, execution time of the test is reduced to a quarter as compared with other test methods where test data are written in and read out of each memory cell one by one.
With the recent development in large-capacity semiconductor memory devices, however, the test time has been evidently increased. Therefore, according to the conventional multi-bit test mode, satisfying reduction in test time and thus in test cost can hardly be achieved any longer.
Therefore, as a technique which allows a drastic reduction in test time as compared with the conventional multi-bit test mode, a line mode test in has been proposed.
In an article by J. Inoue et al., entitled "PARALLEL TESTING TECHNOLOGY FOR VLSI MEMORIES", ITC Proceedings., 1987, pp. 1066-1071; an article entitled "TECHNOLOGY FOR INCREASING TEST EFFICIENCY SUITABLE FOR VERY LARGE CAPACITY MEMORIES", 1987 National Conference 165 of Semiconductor Materials Section of Institute of Electronics, Information and Communication Engineers of Japan, pp. 166, the line mode test is disclosed. All memory cells connected to a word line are simultaneously tested by introducing an on-chip test circuit.
FIG. 19B is a circuit diagram showing a structure of a memory comprising an on-chip test circuit shown in the latter document.
First, for example, "H" and "L" level data are respectively applied to the write lines W and W, and a potential on the write control line WC is raised to the "H" level. Consequently, the transistors Q11 to Q14 are turned on, so that potentials on the bit lines B1 and B2 become the "H" level and the potentials on the bit lines B1 and B2 become the "L" level. When a potential on the word line WL1 is raised to the "H" level, "H" level data are respectively written into memory cells M1 and M3. After writing, the potentials on the word line WL1 and the write control line WC are brought to the "L" level.
Thereafter, when the potential on the word line WL1 is raised to the "H" level, the data stored in the memory cells M1 and M3 are respectively read out onto the bit lines B1 and B2. Data on the bit line pairs B1, B1 and B2, B2 are amplified by a sense amplifier (not shown). Then, "L" and "H" level data are respectively applied to the write lines W and W.
When the data read out from the memory cells M1 and M3 are at the "H" level, the potentials on the bit lines B1 and B2 become the "H" level, and the potentials on the bit lines B1 and B2 become the "L" level. Consequently, the transistors Q15 and Q17 are turned on, so that both potentials of nodes N11 and N12 become the "L" level. Therefore, the transistors Q19 and Q20 are turned off, so that the node N13 precharged in advance by the precharge circuit 110 is not discharged. Thus, an "L" level flag signal is outputted to a detection signal output line DS.
It is assumed here that the memory cell M1, for example, is defective. In this case, the data read out from the memory cells M1 and M3 respectively become the "L" and "H" levels, although "H" level data were written in the memory cells M1 and M3. Consequently, the potentials on the bit lines B1 and B1 respectively become the "L" and "H" levels. When "L" and "H" level data are respectively applied to the write lines W and W, the transistor Q16 is turned on, so that the node N11 is charged at the "H" level. Consequently, the transistor Q19 is turned on, so that the node N13 is discharged at the "L" level. As a result, an "H" level flag signal indicating an error is outputted from the detection signal output line DS.
As described in the foregoing, in the above described line mode test, data are applied to the write lines W and W and then, the data are written into a row of memory cells connected to a selected word line. As a result, the same data are written in the row of memory cells. The data are read out from the row of memory cells, and data opposite to the data previously applied to the write lines W and W are respectively applied to the write lines W and W. When data read out from a row of memory cells all match data previously written in the row of memory cells, an "L" level flag signal is outputted from the detection signal output line DS. On the other hand, when at least one memory cell out of a row of memory cells connected to one word line is defective so that data read out from the memory cell does not match data previously written in the memory cell, an "H" level flag signal is outputted from the detection signal output line DS.
According to this line mode test, all the memory cells connected to one word line are simultaneously tested, and this enables a simultaneous test of a larger number of bits than in the case of the multi-bit test mode. Accordingly, a considerable reduction in test mode can be expected.
In recent years, semiconductor memory devices have come to be implemented largely as having a four-bit word organization (X4 organization), an eight-bit word organization (X8 organization) and the like on the same chip as well as a one-bit word organization(X1 organization) only. Accordingly, additional test mode circuits corresponding to those organizations are required. In order to apply the above-mentioned line mode test to a variety of semiconductor memory devices, provision of peripheral circuits such as I/O control circuit and test mode setting circuit that have been adapted to the respective semiconductor memory devices is desired.
However, it can hardly be said that specific techniques for applying the line mode test to a variety of semiconductor memory devices, and such peripheral circuits or the like have been fully developed.